There has in the recent past been extensive work in the art of digital and analog charge coupled devices and systems. In this technology, charge packets are transferred along a semiconductor substrate from one electrode to another at high speed, with low power requirements, and within an extremely dense circuit configuration. In digital systems using charge coupled devices, the presence of a charge packet can represent one arbitrary binary value, generally chosen for convenience as binary "1" so that the absence of a charge packet then represents a binary "0".
Although the charge coupled device has relatively high efficiency, in preservation and retention of the integrity of a charge packet, leakage losses and transfer losses cannot be avoided, and the charge coupled devices must be used as dynamic elements. That is, charges are repetitively transferred along a chain of such devices, with logical gating functions and arithmetic functions being performed during the serial transfer. As the charge packets are transferred they are diminished in size due to the losses, and care must be taken to avoid dissipation of charge to a level at which an error is likely to occur in detection of the presence of the charge packet. To this end, many attempts have been made to design regenerator circuits, also sometimes referred to as refresh circuits, which respond to the presence of a diminished charge packet by generating a full charge packet. A particularly advantageous regenerator circuit, capable of use in providing a variety of concurrent logical functions, is described in a previously filed application of the present inventor entitled "Regenerator Circuit", Ser. No. 856,780, filed Dec. 2, 1977, now U.S. Pat. 4,135,104 issued Jan. 16, 1979, and assigned to the assignee of the present invention.
The dynamic transfer of charge packets along a series of electrodes is characteristic of a serial digital data handling system. Thus charge coupled devices employ dynamic storages, such as recirculating shift registers, to retain words and values for further processing. This imposes a penalty on the systems designer, and on the data rate achievable with the system, because it is often not desirable to accept the delay inherent in waiting for a word retained in a recirculating shift register to be returned to the index position. It is common in other circuit technology to utilize latch circuits, which are set to a given value and which retain that binary value until such time as reset, and this expedient has many potential applications in digital charge coupled systems. The ability to store, and make available at every clock time, a single bit of information, can be very useful. Preferably, however, both the digital value and its complement are provided, and there is no degeneration of the output charge packet despite the length of the interval involved.